1. Field of the Invention
This invention relates to high voltage CMOS integrated circuits/processes and more particularly to low voltage controlling devices therefor.
2. Description of Related Art
Z. Parpia et al "A Novel CMOS-Compatible High-Voltage Transistor Structure" IEEE Trans Electron Devices, Vol. ED-33, pp. 1948-1952 (December 1986) (reprint pages 116-120) describes a process wherein there is a polysilicon gate lithography alignment problem with the P- region. In LSI technology the P-well P-region is always the first step, the device channel region is in the P-well region or under the polysilicon gate, so the layout must have a longer channel to prevent the polysilicon layer misalignment form the P-well region.
R. Jayaraman et al "Comparison of High Voltage Devices for Power Integrated Circuits" pp. IEDM 84 258-261 (1984) describes a process wherein the P- implant (which is always the P-well implant is performed before the metal gate is formed. The reason that forming the gate after the P- implant is a disadvantage is that although it is the metal gate, the alignment problem remains, so the layout must have a longer channel length.
Note that in the Parpia et al and Jayaraman et al the device structures are implemented in CMOS, so the source side cannot be operated at a high voltage.
In prior art high voltage device structures, although there is an N- guard in the NMOS device, it has to be added with an additional mask. In PMOS devices, the P- well is used as the guard region by modifying the doping thereof, and the current driving capacity is limited by that modified doping of the P- well.